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Writing clean and timing accurate HDL, with proper FSMs is way more difficult than botching up a VGA controller. This seems counter intuitive but the VGA timings are tolerant enough to allow for small errors. Even getting a clock divider cycle accurate was a challenge on itself

The book shows how to write self-testing benches, it's way easier than forcing signals in Modelsim! I've learned a lot writing testbenches for this project and others exercises! I also learnt that HDL that can be simulated won't necessarily synthesize, this was new !

I want to implement some more funny hardware before diving into the real challenge of this book : micro-architecture and RISC-V design. It is said that designing a CPU is a rite of passage for every EE, I can't wait !