A. Schilling

First DDR5 Kit with EXPO ULL just arrived. Let’s see how the fine tuned sub-timings compared to the manuell optimization will work out.

"Sub-1nm" chip technology by @IBMResearch. IBM nanostack architecture: Two transistors stacked and bonded together. Each transistor consists of three nanosheets with a thickness of 5 nm thick or the equivalent to about 15 rows of atoms. newsroom.ibm.com/2026-06-25-i...

My colleague did review the Noctua NL-LC1, the first all-in-one cooler from the air cooling and fan specialist. In a nutshell: Impressive! www.hardwareluxx.de/index.php/ar...

The SiPearl Rhea1 is now in a 12-week functional bring-up phase. It's using 61 billion transistors and is manufactured in N6 at TSMC. sipearl.com/rhea1

It's not a new pictures, but I can't stress enough just how amazing IBM's 300 mm wafer with quantum chips looks!

Does it show how old I am if I like a design like this?

10 years ago 💚💚💚

Why? Why not? Will have some time with four Arc Pro B70 in a Battlematrix workstation.

Testing some Intel Arc Pro B70

VSORA Jotunn8 - 8 compute chiplets - 8 HBM3E - TSMC CoWoS-S packaging - 500 W TDP The package is just a dummy right now. Production is ramping up right now. We will have to wait until MLPerf Inference v6.1 to see how it compares to the competition.

Not only the GPUs are doing the heavy lifting.

Four extra cores and a little software magic: Intel Core Ultra 5 250K Plus and Core Ultra 7 270K Plus review: www.hardwareluxx.de/index.php/ar...

This excellent video by Scott Manley explores how the thermal balance of spacecraft works and what it would take to design a spacecraft capable of dissipating the heat generated by space-based data centers. www.youtube.com/watch?v=FlQY...

Imec starts installing of its ASML EXE:5200 High NA EUV system in its 300 mm clean room in Leuven. Qualification should be finished in Q4 2026.

Since I’m currently looking into 200S Boost again for various reasons, I came across this fantastic German translation. "Die" (Die-2-Die) can be translated to "Stirb" in German which means "death" or "pass away". So it's a Death-to-Death-Interface.

20 years of CUDA and I was there, when it was born. It was a different NVIDIA, it was a different Jensen ;) #GTC2026 #CUDA

Comparison of the logic boards of the new MacBook Neo with the iPhone 16 Pro which is using the same SoC as well as the MacBook Air with M3. Source: youtu.be/PbPCGqoBB4Y

Even though DDR prices are not going up anymore, this shows escalation stage 1 and stage 2 when it comes to memory being not affordable anymore.

Intel Heracles, a FHE accelerator build in Intel 3

Core Ultra 7 270K Plus vs Core Ultra 7 265K Core Ultra 5 250K Plus vs Core Ultra 5 245K But be careful: Plus SKUs did use DDR5-7200 while the non refresh SKUs did use DDR5-6400. It's legit in terms of MC verification, but keep it in mind when seeing these numbers.

Samples already arrived.

Intel just announced the Core Ultra 200S Plus SKUs. Two additional efficiency cores and +900 MHz for the D2D interface. www.hardwareluxx.de/index.php/ne...

Today I saw my first meteorite burn up in the atmosphere. What a spectacle!

Something to play around with in the coming days.

These are tools, that should not really exist, but for certain reasons, in some cases there is at least a desire to use them. We had a look at the Aqua Computer Ampinel and Thermal Grizzly WireView Pro II – do show the features and limitations: www.hardwareluxx.de/index.php/ar...

So we now have the Compute Tile (Intel 18A, first wafer) and Base Tile (Intel 3, second wafer), but we are still missing the I/O Tile (Intel 7) for Clearwater Forest.

#Ampinel by #AquaComputer working hard to balance a faulty 12V-2x6 cable at 600 watts. You can see how the MOSFETs of the balancing electronics are increasing the electrical resistance to regulate inequalities to a certain degree.

AMD PR gave the answer a little later. There are also non-PRO SKUs.

Ryzen AI PRO 400 is not only limited to the PRO segment with regard to the target group, but also in terms of the number of CPU cores and CUs. But there are still renderings without the "PRO" naming floating around with this announcement. So there is still hope for a 8000G successor.

Like Samsung with Fab P5, SK Hynix is also planing a three story cleanroom structural framing that fits up to six cleanrooms in one building of the Yongin semiconductor cluster. Opening of the first cleanroom is expected to be moved up from May to February 2027. news.skhynix.com/new-facility...

Something special arrived today. @msigaming.bsky.social GeForce RTX 5090 Lightning Z and finally we to see something, that should have been there from the beginning: Two 12V-2x6 connectors. 0031 / 1,300 www.hardwareluxx.de/index.php/ne...

A community member of Hardwarelxx developed a mod for the black ASUS ROG Astral RTX 5090 to flash it with the Matrix VBIOS. Great work and nice to these kind of enthusiasm. www.hardwareluxx.de/index.php/ne...

Review drop: AMD Ryzen 7 9850X3D Coming from the Ryzen 7 9800X3D, this is obviously not a sensible upgrade path, but even if it were, the higher power consumption is disproportionate to the additional performance. www.hardwareluxx.de/index.php/ar...

Microsoft Maia 200 is deployed for Azure - 3 nm TSMC - 140 billion transistors - 750 W TDP - 216 GB HBM3e at 7 TB/s - 272 MB SRAM - 10 PFLOPS FP4 - 5 PLOPS FP8

Retesting some CPUs for a reason …

Intel Core Ultra X9 388H C2C Latency You can easily distinguish between the P, E and LPE core clusters – although the LPE cores are now on the same compute tile. www.hardwareluxx.de/index.php/ar...

No die shot today, but I did brick build an ASDS with a landed Falcon 9 booster today. Would make a nice background addition to your filming set @djsnm.bsky.social.

The recurring historical chart showing TSMC's revenue by technology.

Since there appears to be a demand for DDR3 in certain markets, I have opened my old treasure chest. Any offers?

Those small silicon slices that, are visible left and right from the two IODs of Venice, must serve a purpose of signal integrity, right?