Greg

Greg

@gregdavill.bsky.social

Electronics engineer. RISC-V ASICs at IQonIC Works ๐Ÿง™โ€โ™‚๏ธ (He/Him) I also take macro photos of electronics

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Hi ๐Ÿ‘‹ I'm Greg, hardware engineer. I enjoy designing and building open source hardware projects. along with taking macro photos to document the process. Previously at a startup I used FPGAs and thermal LWIR cameras to map bushfires from aircraft Currently doing RISC-V ASIC things at IQonIC Works

Apart from the 3d print tolerance not being great at these sizes and breaking a few of these R50-2W7 sleeves getting them in. A 3d printed bed-of nails jig work surprisingly well for an afternoon build.

This is intended for debugging and attachment to test-points on a PCB. I've not bothered with a "proper" clamping setup, screws on each corner works well here.

I fixed a damaged USB-A port on a PS5 this week. The most tedious part was the 42 security trox screws encasing an EMI/Heat shield to the motherboard. ๐Ÿ™ƒ

Not my neatest work, but it works. This wire's pvc melts super quickly, so soldering can be a challenge. But I still prefer having the colours ๐Ÿ™‚ A quick 3d print to hold the wires avoids strain

Quick weekend project to put enclosures over my various Glasgow prototypes. Teaching myself the "configurations" feature in fusion to handle slightly component placement differences between various Cx versions.

First samples on the first run from wafer.space! There is a disclaimer with these parts, that only ~80% are fully bonded successfully. This could be marketed as a feature, an air gapped solution using state of the art wireless bond wires. ๐Ÿ˜œ

LEDs โ‡๏ธ These are about all on at about the perfect brightness for visual indication. But my standard macro photography process (off camera flash) just floods so much extra light that these appear really dim.

Some BGA footprints are distinct enough to act like a fingerprint for the part. If you've used this part on a board design before you'll likely recognise it. ๐Ÿ˜‰

I'd forgotten that the ECP5-25F doesn't have all the I/O, and 4 or so pins that are on the 45/85F are N/C on the 25F. I just happened to use one of these for the ULPI interface. ๐Ÿฅฒ Bodge wire to the rescue! Now we're enumerating again! USB boot loader in gateware, takes up ~15% of the device

These two boards have the same BGA geometry defined in their gerbers. For some reason JLCs DFM adjustments have expanded all the "via in pad" connections. Makes for an interesting visual effect.

The bodge works! A DFF in front of the ECP5's FPGA SPI configuration port before a mix leading to FLASH and PSRAM. Enabling an initial jump through FLASH where the clock frequency is bumped and QSPI entered. This now fixes an issue violating the PSRAM's tCE<8us requirement.

I've been using KiCad 9's new table features to aid in schematic documentation. I guess it makes sense.. But still puzzled me for a moment that you can perform a vertical/horizontal mirror on a single cell. ๐Ÿ™ƒ

Glad I can jump back in the timeline. Found the culprit! Top object is an imported PCB, arcs on the board outline get converted to straight-line segments when it's exported from KiCad. The purple lines are projected from this PCB outline. Then I've applied an offset to account for tolerance.