Flux

Flux

@willflux.bsky.social

Only hardware makes it possible! FPGA, RISC-V, 68K, OS, graphics, demos, permacomputing http://projectf.io | http://systemtalk.org

353 followers177 following402 posts

If you're working with ECP5 #FPGA, I recommend learning how to control the PLLs to set your own clock frequencies, for example, to generate video signals or interface with DRAM. projectf.io/posts/ecp5-f... PS. Hand written blog with no ads or tracking. Just content. Happy #FPGAFriday 🕰️

projectf.ioECP5 FPGA Clock GenerationYosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL (phase-locked loop), you’re stuck running at the speed of your dev board oscillator. This post outl...

New (secondhand) book to help me develop 🏝️Isle.Computer floating point in #riscv asm. Subnormals seem much easier in software than hardware. 😄

Fascinated Wikipedia clicking always leads to knowledge. Whether this is worthwhile knowledge is left as an exercise for the reader. “At one stage in 1981, three of the top ten best selling books in the US were books on solving Rubik's Cube...”

“The plot of the 1971 comedy film Lady Liberty, starring Sophia Loren, is based on the United States ban on mortadella.”

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demos in the 1990s: chrome sphere on chessboard demos in the 2020s: chrome sphere in dimly lit room

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Replying to @willflux.bsky.social

Can you help? #FPGA I'd like to collect some Isle.Computer Verilator simulation performance from a range of systems. Please run the Verilator simulation of the Isle ch07 design, setting conf.bench_frames = 100; in main_ch07.cpp. Thank you. ☺️ See github.com/projf/isle/t... for instructions.

github.comisle/boards/verilator at main · projf/isleIsle FPGA Computer. Contribute to projf/isle development by creating an account on GitHub.

Both my M1 MacBook Air and Framework i5-1240P Linux laptop get 18.5 FPS (165 ns/cycle) with ch07. My Linux laptop is much faster in performance mode than balanced. The simulation is single threaded. So, I'm particularly interested to see how fast the Ryzen 9000 and latest Apple Silicon are.

🏝️ Isle.Computer is my #FPGA computer from scratch. Exciting new features have been in short supply of late due to life and spending the time I have on improving existing designs/Verilog. I'm now getting back to: * Display Device * Debug Monitor * Dynamic devices with MMIO * Codeberg migration

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Deleting unneeded hardware is satisfying. I realised my degenerate triangle handling logic is no longer needed. Triangles where all vertices are coincident, or in a line, render correctly. 📐

Quick 🏝️ Isle.Computer status update. The latest Isle design is already merged in git. I'm currently writing the next blog post. Once that's live, I plan to work on the debug monitor and migration to Codeberg.

Verilog hates you. If reg [7:0] wptr; and wptr=255 these expressions are completely different: wptr + 1 == 0 wptr + 1'b1 == 0 I blogged about this yet it still caught me out: "Verilog uses the width of the widest operand when evaluating an expression". The width of 1 is 32 bits because #Verilog.

🏝️ Isle.Computer is my #FPGA computer from scratch. Exciting new features have been in short supply of late due to life and spending the time I have on improving existing designs/Verilog. I'm now getting back to: * Display Device * Debug Monitor * Dynamic devices with MMIO * Codeberg migration

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Looks like I've found a real hardware rendering bug. I've only tested this in Verilator/SDL sim so far, but time for me for me to call it a night. I can check it on FPGA when I'm back at my desk. 😴

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Temperatures provisionally reached 38.1°C at Kew Gardens, making it the hottest day of the year so far. This is the second time this year we have reached 38°C. The only other time this has happened twice in one year was in 2022. It also makes it the 5th hottest day on record.

🏝️ Isle.Computer is my #FPGA computer from scratch. Exciting new features have been in short supply of late due to life and spending the time I have on improving existing designs/Verilog. I'm now getting back to: * Display Device * Debug Monitor * Dynamic devices with MMIO * Codeberg migration

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It's too hot to think clearly. 🥵 While working on my hardware graphics engine, I was dismayed to discover a new hardware scrolling bug. On closer inspection it turns out to be an error in my RISC-V asm. ☺️ You can see the broken version running here in simulation.

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The UK will experience a partial solar eclipse on Wednesday 12 August. The extent of the Sun's coverage and the timing of maximum obscuration will differ across the country. Never look directly at the sun; use a pinhole projector or certified eclipse glasses to view it.

🏝️ Isle.Computer is my #FPGA computer from scratch. Exciting new features have been in short supply of late due to life and spending the time I have on improving existing designs/Verilog. I'm now getting back to: * Display Device * Debug Monitor * Dynamic devices with MMIO * Codeberg migration

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Oh no, there's a translation bug in my hardware 2D drawing engine... wait no, my docs aren't clear enough (even to me). Translation only affects coordinates set *after*. 😮‍💨 Docs revised. Now I can move onto CPU controlled animation testing.

The Earthrise drawing engine assembler now outputs memory offsets and the mnemonics assembled. The drawing engine uses 16-bit instructions, but a 32-bit bus to match the 32-bit RISC-V CPU. While I'm big endian at (68K) heart, Earthrise is little endian to match RISC-V.

🏝️ Isle.Computer is my #FPGA computer from scratch. Exciting new features have been in short supply of late due to life and spending the time I have on improving existing designs/Verilog. I'm now getting back to: * Display Device * Debug Monitor * Dynamic devices with MMIO * Codeberg migration

View full thread

🏝️ Isle.Computer doesn't have interrupts yet, but catching bus faults is still handy, especially when running software under Verilator simulation. Here's the code I worked on this morning. #FPGA

Done a bit of work on the 🏝️ Isle.Computer graphics devices today. Here's a 16 colour compositor test running under simulation. #FPGA

🏝️ Isle.Computer is my #FPGA computer from scratch. Exciting new features have been in short supply of late due to life and spending the time I have on improving existing designs/Verilog. I'm now getting back to: * Display Device * Debug Monitor * Dynamic devices with MMIO * Codeberg migration

The display device composites different graphics together, e.g. text mode and bitmap layers, with scrolling, transparency and double buffering. The debug monitor lets you debug from the inside, wozmon style. Dynamic MMIO devices allow hardware to automatically work in different "slots".

I've snuck in a little work on the display device. Getting the display control signals to work across hardware modules, hardware registers, and software takes some doing, especially after recent renaming and refactoring. Having scrolling and transparency under software control is fun though. ☺️