Daniel Estévez

New blog post: A high sensitivity ADS-B receiver. I present a new ADS-B receiver written in Rust that outperforms existing open source receivers such as readsb: ~3x more messages in typical real world terrestrial scenarios and ~2000x more in simulated LEO scenarios.

Additionally, I explain how I have used AI extensively during this project, not to write code, but to help me by reviewing my code, debugging failed unit tests, proposing new unit tests and doing online searches. The goal in using AI here is to write code better, not faster.

New blog post: A high sensitivity ADS-B receiver. I present a new ADS-B receiver written in Rust that outperforms existing open source receivers such as readsb: ~3x more messages in typical real world terrestrial scenarios and ~2000x more in simulated LEO scenarios.

The decoder sensitivity in AWGN is only 0.8 dB worse than the coherent demodulation theoretical limit.

New blog post: A high sensitivity ADS-B receiver. I present a new ADS-B receiver written in Rust that outperforms existing open source receivers such as readsb: ~3x more messages in typical real world terrestrial scenarios and ~2000x more in simulated LEO scenarios.

New blog post: Decoding the Roman Space Telescope. On August 31 I observed the Roman telescope S-band telemetry with the Allen Telescope Array some time after launch. This post is a summary of the observation, including the telemetry decode and a preliminary analysis.

New blog post: On matched filtering in the presence of carrier frequency offset. In this short maths note I explain how to tweak a matched filter to improve the SNR when there is carrier frequency offset.

I close with some remarks about usage in practice. When the frequency grid spacing is narrower than the inverse of the number of samples, the conventional matched filter performs quite well and the DPSS-windowing improvement is small. For larger spacings it provides a minor gain.

New blog post: On matched filtering in the presence of carrier frequency offset. In this short maths note I explain how to tweak a matched filter to improve the SNR when there is carrier frequency offset.

Concretely, I explain how to maximize the average SNR when a bank of filters spaced on a regular grid of frequencies is used and the carrier frequency offset is distributed uniformly.

New blog post: X-engine correlator on a Ryzen NPU. A few months ago I posted about the basics of NPUs in Ryzen AI chips. I wanted to tackle a real-world problem to get more experience, so I've implemented an X-engine correlator like the ones used in radio astronomy.

Next I consider the data flow through the whole NPU array. This leads to a design of the Ethernet packets that the X-engine ingests. There is a tradeoff between having the data in the order that the X-engine prefers and having it in an order that is easy to generate in the PFBs.

New blog post: X-engine correlator on a Ryzen NPU. A few months ago I posted about the basics of NPUs in Ryzen AI chips. I wanted to tackle a real-world problem to get more experience, so I've implemented an X-engine correlator like the ones used in radio astronomy.

In the blog post I go over all the details of the bottom-up design and implementation and all the challenges I found. I explain how to do some back-of-the-envelope calculations to estimate performance before we begin coding.

New blog post: X-engine correlator on a Ryzen NPU. A few months ago I posted about the basics of NPUs in Ryzen AI chips. I wanted to tackle a real-world problem to get more experience, so I've implemented an X-engine correlator like the ones used in radio astronomy.

Testing this design on a Ryzen laptop is just for prototyping and learning. The X-engine ingests 65.5 GB/s and there is no way that I can input that amount of data from the outside world into a laptop (this Ryzen SoC has 16x PCIe 4.0, which would give 31.5 GB/s).

New blog post: X-engine correlator on a Ryzen NPU. A few months ago I posted about the basics of NPUs in Ryzen AI chips. I wanted to tackle a real-world problem to get more experience, so I've implemented an X-engine correlator like the ones used in radio astronomy.

NPUs are essentially arrays of vector processors intended to perform large matrix multiplications very fast, and an X-engine does just that: a large matrix product. However, getting the X-engine running right on the NPU is trickier than it sounds, due to many low-level factors.

This Sentinel-2 infrared image from yesterday shows the extent of the Madrid wildfires, which are now stable and do not show any smoke in satellite imagery. The false colour map shows two shortwave infrared bands (B12 and B11) in red and blue, and near infrared (B8) in green.

Burnt areas appear in dark red or purple, due to the dryness causing lower water absorption in shortwave infrared, and higher absorption in near infrared caused by soot. Healthy vegetation appears in green due to the high reflectance of leaf cellular structures in near infrared.

Muon Space is looking for an FPGA engineer for RF signal processing. Join a team of FPGA engineers and RF DSP engineers including myself to build state of the art RF instruments. Ability to access ITAR/EAR information required. DM me if you are interested or have questions.

New blog post: @openresearch.institute.web.brid.gy's Lunar descent CTF. This is my solution to a CTF that simulates the Ka-band radio altimeter of Chandrayaan-3. The goal is to understand and fix a bug in the measurement processing logic.

New blog post: PLL coefficients for rate-only feedback. A couple years ago I wrote a post that extends a paper of Stephens and Thomas where they model PLLs in discrete time rather than transforming a continuous-time design.

I showed that the loop coefficients for an order 2 loop with supercritical damping and phase/phase-rate update have explicit formulas that are obtained by solving a cubic equation. Now I treat the rate-only update case, showing that it leads to a degree 6 equation.

New blog post: An update about Tianwen-2 telemetry. This is a quick update about Tianwen-2 telemetry decoding. First, I've figured out the format of the timestamps included in AOS frames. I explain what was confusing me yesterday.

More fun with the Ryzen AI NPU. I'm working on a more complex algorithm, and I'm seeing memory stalls that make me lose one cycle in each iteration. It turns out that the data memory of compute tiles is organized as 8x 256-bit wide 8 KiB memory banks.

Each bank supports one simultaneous access, and every two banks are interleaved to form a 512-bit wide 16 KiB virtual bank. The two load units of the processor can perform simultaneous 512-bit loads only if these target different 16 KiB banks.