Rohan makes ASICs 🛠️

We have the silicon. And it's working🎉🍾 ROM-less CORDIC engine hooked up to an SPI master @ 22 MHz. Thanks @tinytapeout.com We pulled it off! Cheers to @aksharvastarpara.bsky.social, Rohan Sundar, @deeempak.bsky.social, Praveen, Devang, Rishik, and Tejas.

Rohan makes ASICs 🛠️@rohan-devarc.bsky.social

Low power math within few clock cycles. Imagine it, then put it into silicon. Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks. Check - t.co/vBGGA2i0uX Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.

5 Sept

Thanks @tinytapeout.com 🙌

Rohan makes ASICs 🛠️ reposted

bitbangingbytes.substack.comFrom Taylor Series to Silicon: Building and Debugging a ROM-less CORDICHow we fixed our chip by lying to it

17 Aug

And then the fun part started: debugging the actual chip. 😅 Full story bitbangingbytes.substack.com/p/from-taylo...

bitbangingbytes.substack.comFrom Taylor Series to Silicon: Building and Debugging a ROM-less CORDICHow we fixed our chip by lying to it

17 Aug

And then the fun part started: debugging the actual chip. 😅 Full story bitbangingbytes.substack.com/p/from-taylo...

11 Aug

Software has bugs. Silicon has consequences. - An RTL constant that happened to be an input saved the maths. - An SPI phase bit that host could flip saved the link. Both accidents. Both saved the chip. Either Design for testability or don't bother taping out.

Rohan makes ASICs 🛠️@rohan-devarc.bsky.social

github.comGitHub - rohanverma94/cordic_romless_v1_test_harness: Test harness for ASIC testing of CORDIC design.Test harness for ASIC testing of CORDIC design. Contribute to rohanverma94/cordic_romless_v1_test_harness development by creating an account on GitHub.

7 Aug

Do check calibration and silicon characterization report - github.com/rohanverma94...

4 Aug

POV: you've blamed the testbench, the tool, the PDK, and the moon. Day 1: "It worked in simulation." Day 2: "It's probably a timing issue." Day 3: "It's probably haunted." Day 4: it was the RTL.

Rohan makes ASICs 🛠️ reposted

deeempak.bsky.social

@deeempak.bsky.social

The first tapeout i was a part of feels good to see it working 😁😁

Rohan makes ASICs 🛠️@rohan-devarc.bsky.social

Rohan makes ASICs 🛠️@rohan-devarc.bsky.social

Coarse measurement with 100 angles on full 0–360° sweep: Mean absolute error 3.53e-4 (1.4 LSB), RMS error 4.09e-4 Fine measurement with 250 angles on full 0–360° sweep: Mean absolute error 4.19e-4 (1.7 LSB), RMS error 5.20e-4

24 July

The SCL 1.2µm PDK just dropped on eChipHub, but it's gated to students and professionals in India. verify.echiphub.in

20 July

have you seen god?

Had fun doing bring up for XC2064, the first FPGA ever made with 64 CLBs. Scale is so small that, I was able to use Logic Cell Array editor to manually place and route the design by hand, no automation.

That moment when you get a clean edge transition with a clean clock. xilinx xc2064 was indeed a wonderful device. It was quite tricky to get the bitstream working.

righto.comReverse-engineering the first FPGA chip, the XC2064A Field-Programmable Gate Array (FPGA) can implement arbitrary digital logic, anything from a microprocessor to a video generator or crypt...

Wild part is the config pins (M0, M1, M2, CCLK, DONE) still work the same way as on the Xilinx 7 series chips. I wrote a sketch based on arduino nano to offload the bitstream to XC2064. This blog is genuinely a great motivation to understand how far FPGAs have come - www.righto.com/2020/09/reve...

13 June

sovereign AI was a scam New Internet was a scam Web3 was a scam AGI by 2025 was a scam resistors are real MIM cap is real transistors are real kT/C noise is eternal Kirchhoff never lied to you parasitic capacitance will outlive your startup

24 May

Why stop at verilog gaming? Everything from sprites, controller and character animation is a state machine in itself. Now imagine putting a whole rasterization pipeline in there.

Rohan makes ASICs 🛠️@rohan-devarc.bsky.social

Want to play? 😋 Made with verilog.

7 Apr

Want to play? 😋 Made with verilog.

3 Apr

So this one guy submitted a very cool entry for @tinytapeout.com's demoscene competition. I really liked the gradient and banner and whole starry sky implemented with LFSR. It's crazy that we can put all of this in one or two tiles.

26 Mar

cooking an asic for demoscene competition 🤘 @tinytapeout.com

4 Mar

These are bare dies of the Kintex-7 XC7K325T and its pin-compatible Chinese clone, the JFM7K325T from Fudan Micro. Only difference is that GTX transceivers of JFM7K325T behave differently, so the xilinx pcie core wouldn't work by default.

4 Mar

The real question is that where do you draw the line on democratizing silicon?

28 Feb

ANTHROPIC !!!! 👏👏

20 Feb

BREAKING TRUMP ANNOUNCES MAGAS WILL BECOME 10% MORE STUPID & BELOW THE AVERAGE IQ.

Rohan makes ASICs 🛠️ reposted

21 Jan

Fly through video for ROM-less Cordic Engine design. This design is on TTSKY25A shuttle by @tinytapeout.com Made easy with BlenderGDS plugin - github.com/aesc-silicon... @mattvenn.net @urishaked.bsky.social @aksharvastarpara.bsky.social

21 Jan

Rohan makes ASICs 🛠️ reposted

15 Jan

Replying to @rohan-devarc.bsky.social

welcome to our cordic city!!

15 Jan

Yes, that’s a GDSII render. Yes, it’s inside Blender. Yes, it’s our design on TTSKY25A chip. @tinytapeout.com @mattvenn.net @urishaked.bsky.social

15 Jan

welcome to our cordic city!!

28 Oct 2025

This is the DCJ11 PDP-11 processor, built using the old-school ZMOS tech, a 3  μm NMOS process with two interconnect layers. It was one of the first NMOS processes to use separate metal layers for local connections and global signals.

28 Oct 2025

Back in the day, NMOS chips used only one metal layer, so designers had to squeeze all the wiring onto a single surface. Metal 1: used for local interconnects, this allowed short and dense wiring. Metal 2: used for global signals like buses, clocks, power.

28 Oct 2025

Innovation in ZMOS process node led to development of modern CMOS and BiCMOS process node where we have 20 metal layers. For instance, Sky130A 130nm process node have upto 5 metal layers. bsky.app/profile/roha...

Rohan makes ASICs 🛠️@rohan-devarc.bsky.social

26 Oct 2025

This looks like a matrix. Each one has 128 analog switches. We can do 8x16 analog array with one. So this is actually a analog matrix.

26 Oct 2025

chinese semiconductor industry is creative for sure. Nice idea for analog tapeout for some day.

16 Oct 2025

Google has open sourced its Coral NPU, which uses a 32 bit RISC V core with the Zve32x extension. It supports vector arithmetic on data ≤ 32 bits, making it great for DSP applications. It has been prototyped on a Xilinx Ultrascale Plus FPGA platform. github.com/google-coral...

16 Oct 2025

Note that Zve32x extension works only on integers, it needs Zicsr and Zvl32b base profiles to be implemented first. Although the element size is capped at 32 bits, the wide vector registers (256 bits) still allow multiple elements to be processed simultaneously.

youtu.beTeardown Session 56: wafer.space with Tim AnsellYouTube video by Crowd Supply

16 Oct 2025

And guess what whole hdl for this is written in both system verilog and chisel/scala.

Rohan makes ASICs 🛠️ reposted

Tim 'mithro' Ansell

@mith.ro

30 Sept 2025

Leo Moser and myself will be on @crowdsupply.bsky.social 's Teardown Session talking with @helenleigh.bsky.social about @wafer.space this Thursday (3rd October) - youtu.be/tEOmnN8IAjs

28 Sept 2025

FYI : Original electronic diary was invented by a Indian guy known as Satyan Pitroda, alias Sam Pitroda. He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares. www.computerhistory.org/revolution/m...

pi0cket.bsky.social@pi0cket.bsky.social

I have been playing with the idea of a PCB inlay for the front of the case to add some flair and make the button legends a bit easier to see 😄 looks kinda nice if I do say so myself 🤣 #pi0cket #CL32 #ESP32

Rohan makes ASICs 🛠️ reposted

Tim 'mithro' Ansell

@mith.ro

25 Sept 2025

It was awesome to be on @chrisgammell.bsky.social 's Amp Hour podcast again. Find out more about my latest endeavor to make custom silicon manufacturing accessible and follow @wafer.space and bookmark wafer.space to keep up to date!

Chris Gammell@chrisgammell.bsky.social

What happens when one of the main providers that enables #opensource #silicon to thrive...shuts down? Companies like @mith.ro's new wafer.space jump in and offer an even more compelling option. $7K for 1000 chips on the GlobalFoundries GF180MCU process. Learn more: theamphour.com/703-building...

6 Sept 2025