YosysHQ

The green traces show a chip designer’s worst nightmare! If they take too long to settle, it causes a serious problem that can’t be fixed after a chip is manufactured. Try out my updated metastability explorer tool here: zerotoasiccourse.com/metastability/

Have you upgraded your @yosyshq.com yosys recently? #FPGA 0.49 (Jan 2025): TRELLIS_COMB: 4357 0.64 (May 2026): TRELLIS_COMB: 3682 15% LUT saving with no change in my Verilog design. 👏

$1200 too much for a Vivado license? How about: $0 - Yosys $0 - nextpnr $0 - OpenROAD $30 -Subnautica 2 $30 - Blahaj $180 - Glasgow interface explorer from @crowdsupply.bsky.social $950 -160kum^2 of Sky130 silicon + ASIC from @tinytapeout.com #opensource #FPGA #ASIC

Happy Trans day of visibility from a Tiny Tapeout ASIC!

Join us in just over 3 hours for our 12th Yosys User's Group!

At RF, your circuit stops being “small” compared to the signal - and everything changes. New video interview about RF design, VNAs, simulation, and on-chip antennas. www.youtube.com/watch?v=2xSA...

The last month of my life: BreakingTTAPs This is a custom transport-triggered, 32 bit processor that will be fabricated by GlobalFoundries on their 180nm process (via of wafer.space) I'll make a video at some point, but some high level details here:

What open source ASIC tools am I excited by in 2025? OpenEMS, 3D viewers, Surfer, OpenROAD, and lots more! Check this article for all the links: zerotoasiccourse.com/post/excited... #opensource #ASIC #tools

Ever wanted to try adding formal verification to your project but it seemed too hard or expensive to get started? In this video @mattvenn.net Venn shows you an easy way to get up and running with our open source tools and GitHub actions! youtu.be/Tn5wCOhzfvs #Verification #Formal #OpenSource

You have just 10 days left to get your #ASIC design submitted to our TTSKY25b shuttle! There are still 70 early bird dev kits left, which mean you can do a full custom tapeout for just €185! Get started here: tinytapeout.com

Starting in just over an hour! meet.jit.si/yosys-users-...

Join us tomorrow at 18:00 CEST!

this is me!! very much looking forward to presenting :3 please come join if you're interested in spaceflight/fault-tolerant computing or EDA algorithms! #yosys #eda

Our next #YUG will be with Matt Young, talking about triple modular redundancy. Join us at 18:00 CET / 22:30 IST / 09:00 PT on Thursday 9th October. Sign up to our mailing list to get a reminder before the event: blog.yosyshq.com/newsletter/

Teaching processor design at Telecom Nancy Lesson 1: build your own risc-V processor at home using a FPGA Course notes are here: github.com/BrunoLevy/le...

We are hiring! Both technical and admin, please take a look at our jobs page! www.yosyshq.com/jobs #jobs #hire

In our latest guest blog post, Matt Young introduces an Automated Triple Modular Redundancy EDA Flow for Yosys! blog.yosyshq.com/p/tamara-tow...

Isle 🏝️ is my new #FPGA project. Isle is a simple, modern computer — an open design that encourages tinkering, experimentation, and doing your own thing. I hope to inspire you to come on a journey with me and build your own computer. projectf.io/isle/fpga-co...

Want to help build a crowdsourced microcontroller? You're invited to design peripherals (UARTs, timers, synths, etc.) for a @riscv.org.web.brid.gy chip that will be fabbed for real! Take part for free! tinytapeout.com/competitions...

We have a new home for community discussion around Yosys yosyshq.discourse.group Join us there for questions, support and discussion about our open source EDA tools. #community #opensource #Yosys

We have a new home for community discussion around Yosys yosyshq.discourse.group Join us there for questions, support and discussion about our open source EDA tools. #community #opensource #Yosys

Yes, if yosys and friends didn't exist I probably wouldn't have done any HW side projects, so i'd never have started Spade or Surfer

My thesis is now published online! 🎉 urn.kb.se/resolve?urn=...

IHP25b - our 4th open source chip with IHP is now open for digital design submissions! We’re very happy to have our next shuttle open and we’re already looking forward to seeing another great set of designs manufactured onto custom silicon!

We’re close to making key decisions about future shuttles—and we want your input! 💬 What features matter most? What’s your price ceiling? Take our 2-min survey 👉 forms.gle/EMrSJQ6dmw4P... 🎁 One respondent will win a beautiful 150mm silicon wafer!

Bad AAPL

Good news open-source #FPGA fans, there's a new release of nextpnr (place and route) from @yosyshq.com. The release notes mention "Numerous improvements to Gowin support": github.com/YosysHQ/next...

Join us in a few hours for a talk about ASIC synthesis with Yosys! 18:00 CET / 22:30 IST / 09:00 PT meet.jit.si/yosys-users-...

Simulation is the #ASIC terminology of the week! In the last month, Simulation has been the 35th most popular out of 42 terms.

Looking for a tiny RISC-V core that scales with your needs? We covered FazyRV by Meinhard Kissich in our community spotlight last year: blog.yosyshq.com/p/community-... Now it's been silicon proven on @tinytapeout.com ! www.linkedin.com/posts/meinha...

Insta-follow, nice! Looking forward to your dive in to interesting off the main path of @yosyshq.com bit. Gonna have to figure out what other fpga/yosys/openfpga nerds there are to follow here that I'm missing!

Fearlessly generate your own clocks with Lattice ECP5 #FPGAs and Yosys. Includes worked examples for #ULX3S and easy to adapt to any dev board. Happy #FPGAFriday! @yosyshq.com projectf.io/posts/ecp5-f...

Working on a new #FPGA blog post this evening. I'll be sharing the draft with my sponsors in the next few days. @yosyshq.com "Yosys and nextpnr have excellent support for Lattice ECP5 FPGAs. However, without using the ECP5 PLL, you're stuck running at the speed of your dev board oscillator..."

I taped out a variety of adders on open source silicon and Kogge-Stone adders were the fastest for all widths above 8 bits. Yosys now has plugins to choose which topology you want! Read more here: www.zerotoasiccourse.com/post/instrum...

Very cool work by courk.cc ! Laser fault injection rig used to defeat RP2350 secure boot. Lovely writeup, interactive 3d model views, and uses the open source Glasgow FPGA multitool! courk.cc/rp2350-chall...

Have you ever wondered how Yosys prepares your design for an #FPGA? In the next Yosys Users Group, our own Krystine will walk us through the synth_ice40 command, how it works and what's going on behind the scenes! Monday 16th December at 9:00 PT / 18:00 CET / 22:30 IST

At the beginning of the year Gabriel Gouvine wrote a guest blog post for us about his logic locking plugin for Yosys. He taped out a locked design on Tiny Tapeout 6 and we've just tested it! Blog: blog.yosyshq.com/p/logic-lock... youtu.be/m7MlQ2k8xC8

After a summer break, our user group meetings have resumed again! In our last call, Katharina CeesaySeitz from ETH Zürich presented her work to detect microarchitectural information leakage via hardware timing side channels. Watch her talk on our Youtube channel! www.youtube.com/watch?v=Kxp-...

Video of @mattvenn.net MPW1 chip

1st post on bluesky!